Completion Detecting Carry Select Addition

We present the logic analysis, circuit implementation and verification of a novel selftimed adder scheme based on Carry Select (CS) logic. The preliminary analysis of the variabletime behavior of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimize the average performance. Hence we describe the logic design and full-custom circuit implementation of a completion detecting CS adder by means of precharged CMOS logic. We verify the correct asynchronous operation of the circuit by means of layout level Spice simulation referring to a 0.35 μm CMOS process. The worst case addition time is comparable with existing fastest fixed-time adders, which is a considerable result for a completion detecting technique. The hardware overhead can be limited to 23% over a conventional CS adder. Spice simulation let us estimate an average detected addition time of 1.6 ns for a 64 bit adder, including the pre-charge time. NOTE: This version may contain errors with respect to the final published paper. Please refer to the final publication on IEE Proceedings Prof. Mauro Olivieri Dept. of Electronic Engineering Univ. of Rome “La Sapienza” Via Eudossiana 18 00184 Rome Italy. Tel. +39 06 44585475 Fax +39 06 4742647 Email [email protected]